Electronic circuits, in particular integrated circuits (ICs), are simulated prior to their realization, before the actual fabrication of the masks—required for fabricating integrated circuits—for the individual semiconductor processes. This procedure helps to save costs since malfunctions of the circuit can still be determined prior to realization in order to change the circuit. If the circuit is not examined sufficiently during the design, possible faults may not be identified until after the realization of the circuit or the IC by means of complicated experimental tests, which necessitates subsequent changes in the circuit design, and thus to the circuit layout, and the fabrication of new circuit patterns.
Owing to the complexity of present-day integrated circuits, which comprise up to a few million components, circuit simulation is effected by using computer programs which, in automated fashion, determine voltages and currents in the circuit branches of a circuit depending on input signals present at connections of the circuit. One computer program that is customary for circuit simulation is the circuit simulation program SPICE (EECS Department of the University of California in Berkeley: Homepage: http://www.eecs.berkeley.edu/.SPICE Homepage: http://bwrc.eecs.berkeley.edu/Classes/IcBook/SPICE).
For the simulation using such a program, a so-called netlist is created, which contains information about all the circuit nodes occurring in the circuit to be simulated and the circuit components connected to the respective nodes. In order to simulate the circuit behavior, i.e. in order to calculate the currents and voltages in the circuit, use is made of models of the circuit components to be realized, which are usually stored in a model library that is accessed by the simulation program. The models describe the real behavior of the individual circuit components for example on the basis of the transfer response of the individual circuit components. SPICE models for discrete and integrated components which occur in a circuit to be simulated are usually made available by the manufacturers of said components or the developers of the IC technology used, for example on Internet pages.
The simulation comprises simulating not only normal operating states but also, inter alia, “exceptional states”, such as may occur for example in the event of electrostatic discharges (ESDs) at the connections of the circuit. Said ESDs may occur either without external interconnection, for example as a result of an ungrounded person touching the circuit, or else during operation. In order to determine the robustness of the circuit toward such current pulses occurring as a result of ESD and in order to determine possibly jeopardized circuit components in the circuit, it is necessary, in principle, to simulate the entire circuit including protection structures present, if appropriate, at the connections, in order to be able to change jeopardized circuit regions if appropriate while still at the design stage.
For examining the circuit behavior in the event of ESD interference pulses being applied to the circuit inputs, a so-called transient simulation is required, which determines the temporal profiles of the currents and voltages occurring in the circuit depending on the temporal profile of the interference pulse. For this purpose, the circuit has to be completely simulated for a multiplicity of different input values, which in each case represent temporally successive samples of the interference pulse, in which case, for determining the currents and voltages for each of these input values, it is additionally necessary to take account of the circuit state for the previous input value and the time difference with respect to this previous circuit stage. As the number of components present in the circuit increases and as the temporal resolution increases, this procedure rapidly encounters its limits owing to the requisite high computational capacity.
In order to be able to carry out such simulations with a tenable outlay, developers nowadays “manually” extract presumed jeopardized circuit structures in order to obtain a circuit structure which is reduced with regard to the number of components and for which such a transient simulation can be carried out with tenable computational complexity. However, this manual procedure in the extraction of circuit structures is very prone to error because current paths that may critically influence the circuit behavior in the event of interference pulses can easily be overlooked in complex circuits having a multiplicity of components. Added to this is the fact that precisely parasitic effects may critically influence the circuit behavior in the event of such interference pulses. Although said parasitic effects can be taken into account in the models of the circuit components used for the simulations, they are usually not directly evident from a circuit diagram, which only shows the individual “useful” circuit components of the circuit and which is usually used by developers for manual circuit extraction.
One possibility for automating the search for jeopardized circuit components or circuit sections is described in Baird, M.; Ida, R.: “VerifyESD: A Tool for Efficient Circuit Level ESD Simulations of Mixed-Signal ICs”, EOS/ESD Symposium Proceedings (2000), pages 465-469. The method explained is based on a circuit having two connections between which an ESD pulse is present. The method comprises assigning to all the components present in the circuit in each case a critical voltage that specifies a voltage loading limit for, the respective component, where damage or destruction of the component or at least a current flow through the component must be expected in the event of said limit being exceeded. Resistances and capacitances are replaced by short circuits in this case. The circuit is then examined in automated fashion for all current paths between the two connections and each current path is allocated a critical voltage corresponding to the sum of the critical voltages of all the components present in the current path. If this critical voltage of a path is less than a voltage—which can be predetermined by the user—corresponding for example to the maximum voltage resulting from an ESD pulse, then the respective current path is marked as critical. All current paths marked as critical are then taken over into a reduced circuit on the basis of which exact transient simulations can be carried out.
In this known method, each pair of connections of a component has a fixed critical voltage; therefore, the switching state of a transistor, for instance, or the voltage established at a voltage divider cannot be taken into account. If, by way of example, an output of an inverter realized by two transistors is loaded by an interference pulse, then it is usually the case that one of the two transistors is switched off and one is switched on, to be precise depending on a potential established in transient fashion (e.g. by means of capacitive or resistive voltage dividers) at the input. The voltage that is certainly still harmless thus results e.g. as a sum of the threshold voltage, that is to say the voltage at which the transistor switches on, and the breakdown voltage thereof. When determining the critical voltages, the known algorithm can only assume either turned-off or turned-on transistors, that is to say in the above case must regard either threshold or breakdown voltage as the critical voltage, and thus in any case obtains an incorrect result—with either unnecessarily many or incorrectly too few critical current paths.